1. Field of the Invention
The invention relates to the process of designing and fabricating semiconductor chips. More specifically, the invention relates to a method and an apparatus for controlling rippling during an optical proximity correction (OPC) process, wherein the OPC process compensates for optical effects that arise during the semiconductor fabrication process.
2. Related Art
Recent advances in integrated circuit technology have largely been accomplished by decreasing the feature size of circuit elements on a semiconductor chip. As the feature size of these circuit elements continues to decrease, circuit designers are forced to deal with problems that arise as a consequence of the optical lithography process that is typically used to manufacture integrated circuits. This optical lithography process begins with the formation of a photoresist layer on the surface of a semiconductor wafer. A mask composed of opaque regions, which are formed of chrome, and light-transmissive clear regions, which are generally formed of quartz, is then positioned over this photo resist layer coated wafer. (Note that the term xe2x80x9cmaskxe2x80x9d as used in this specification is meant to include the term xe2x80x9creticle.xe2x80x9d) Light is then shone on the mask from a visible light source, an ultraviolet light source, or more generally some other type of electromagnetic radiation together with suitably adapted masks and lithography equipment.
This light is reduced and focused through an optical system that contains a number of lenses, filters and mirrors. The light passes through the clear regions of the mask and exposes the underlying photoresist layer. At the same time, the light is blocked by opaque regions of the mask, leaving underlying portions of the photoresist layer unexposed.
The exposed photoresist layer is then developed, through chemical removal of either the exposed or non-exposed regions of the photoresist layer. The end result is a semiconductor wafer with a photoresist layer having a desired pattern. This pattern can then be used for etching underlying regions of the wafer.
One problem that arises during the optical lithography process is xe2x80x9cline end shorteningxe2x80x9d and xe2x80x9cpullbackxe2x80x9d. For example, the upper portion of FIG. 1 illustrates a design of a transistor with a polysilicon line 102, running from left to right, that forms a gate region used to electrically couple an upper diffusion region with a lower diffusion region. The lower portion of FIG. 1 illustrates a printed image that results from the design. Note that polysilicon line 102 has been narrowed using optical phase shifting in order to improve the performance of the transistor by reducing the resistance through the gate region.
Also note that because of optical effects and resist pullback there is a significant amount of line end shortening. This line end shortening is due to optical effects that cause the light to expose more of the resist under a line end than under other portions of the line.
In order to compensate for line end shortening, designers often add additional features, such as xe2x80x9chammer heads,xe2x80x9d onto line ends (see top portion of FIG. 2). The upper portion of FIG. 2 illustrates a transistor with a polysilicon line 202, running from left to right, which forms a gate region used to electrically couple an upper diffusion region with a lower diffusion region. A hammer head 204 is included on the end of polysilicon line 202 to compensate for the line end shortening. As is illustrated in the bottom portion of FIG. 2, these additional features can effectively compensate for line end shortening in some situations.
These additional features are typically added to a layout automatically during a process known as optical proximity correction (OPC). For example, FIG. 3 illustrates line end geometry 302 (solid line) prior to OPC and the resulting corrected line end geometry 304 after OPC (dashed line). Note that the corrected line end geometry 304 includes regions with a positive edge bias in which the size of the original geometry 302 is increased, as well as regions of negative edge bias in which the size of the original geometry 302 is decreased.
During the OPC process, edges in the layout are divided into segments at dissection points. Next, the system selects an evaluation point for each segment and then produces a bias for each segment so that a simulated image of the segment matches the target image for the segment at the evaluation point. Referring to FIG. 4, biases are introduced for each segment to produce a layout represented by the dashed line. This layout produces a simulated image represented by the curved line. Note that this simulated image matches the target image at evaluation points 402-404. However, this simulated image has ripples which cause large critical dimension variations in between the evaluation points.
Circuit designers presently deal with rippling by manually adjusting dissection points, evaluation points and segment biases. This manual process is time-consuming and may not be applied consistently to all portions of the layout.
What is needed is a method and an apparatus that automatically controls rippling during the OPC process.
One embodiment of the present invention provides a system that controls rippling caused by optical proximity correction during an optical lithography process for manufacturing an integrated circuit. During operation, the system selects an evaluation point for a given segment, wherein the given segment is located on an edge in the layout of the integrated circuit. The system also selects at least one supplemental evaluation point for the given segment. Next, the system computes a deviation from a target location for the given segment at the evaluation point. The system also computes a supplemental deviation at the supplemental evaluation point. Next, the system adjusts a bias for the given segment, if necessary, based upon the deviation at the evaluation point. The system also calculates a ripple for the given segment based upon the deviation at the evaluation point and the supplemental deviation at the supplemental evaluation point. If this ripple exceeds a threshold value, the system performs a ripple control operation.
In a variation on this embodiment, the system adjusts the bias, if necessary, and performs the ripple control operation, if necessary, for each segment that is part of the layout of the integrated circuit.
In a variation on this embodiment, prior to selecting the evaluation point for the given segment, the system dissects edges in the layout into segments for optical proximity correction purposes.
In a variation on this embodiment, performing the ripple control operation involves performing a refinement operation. This refinement operation involves: selecting additional dissection points for the edge that cause the given segment to be divided into multiple segments; selecting additional evaluation points for the multiple segments; and selecting additional supplemental evaluation points for the multiple segments. The refinement operation also involves adjusting the bias, if necessary, and performing the ripple control operation, if necessary, for each of the multiple segments.
In a variation on this embodiment, selecting additional evaluation points involves using supplemental evaluation points as the additional evaluation points.
In a variation on this embodiment, performing the ripple control operation involves performing a regeneration operation. This regeneration operation involves changing the location of dissection points for the edge to cause the edge to be divided into a different set of segments. It also involves adjusting the bias, if necessary, and performing the ripple control operation, if necessary, for each segment in the different set of segments. Note that changing the location of the dissection points for the edge can involve swapping dissection points and evaluation points.
In a variation on this embodiment, performing the ripple control operation involves controlling the bias for the given segment so that the ripple for the given segment does not exceed the threshold value, wherein as a consequence of controlling the bias a critical dimension for the given segment may not meet specification.
In a variation on this embodiment, computing the deviation for the given segment involves using a model-based technique for computing the deviation.
One embodiment of the present invention produces a system for controlling rippling caused by optical proximity correction during an optical lithography process used in manufacturing an integrated circuit. During operation, the system selects a first evaluation point and one or more additional evaluation points for a given segment, wherein the given segment is located on an edge in the layout of the integrated circuit. Next, the system computes a first deviation from a target location for the given segment at the first evaluation point. The system also computes a second deviation at the second evaluation point. Next, the system adjusts a bias for the given segment, if necessary, based upon multiple deviations at multiple evaluation points, including the first deviation at the first evaluation point and the second deviation at the second evaluation point.
In a variation on this embodiment, both the first evaluation point and the second evaluation point are located on the given segment.
In a variation on this embodiment, the additional evaluation points are located on the given segment or on neighboring segments.
In a variation on this embodiment, the system adjusts the bias, if necessary, for each segment that is part of the layout.
In a variation on this embodiment, the system uses a model-based technique for computing the first deviation and the second deviation.